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1 features ? supply voltage range 3 v to 4.6 v (unregulated) ? auxiliary voltage regulator on-chip ? low current consumption ? few low cost external components ? no mechanical tuning required ? non-blindslot and blindslot operation ? unlimited multislot operation with advanced closed-loop modulation ? supports multiple reference clocks (10.368 mhz/13.824 mhz/20.736 mhz) ? tx preamplifier with 0 dbm output power at 1.9 ghz and ramp-signal generator for sige power amplifier electrostatic sensitive device. observe precautions for handling. description the t2801 is an rf ic for low-power dect applications. the hp-vfqfp-n48- packaged ic is a complete transceiver including image rejection mixer, if amplifier, fm demodulator, baseband filter, rssi, tx preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated vco, tx filter and modulation compensation circuit for advanced closed-loop modulation concept. no mechanical tuning is necessary in production. figure 1. block diagram tank pc rc gf mcc cp vco f : n f : n ctrl logic pd tx / rx switch ir mixer if amp 1 if amp 2 demod bb filter 3-wire bus demod dac rssi tx driver clock data enable rx_on tx_on pu_rx/tx pu_pll tx_data rssi bb_out cf demod if_tank if_in mixer out rf_in tx_out vs_vco cp ld ref_clk vtune vreg vs_reg reg_ctrl vreg_vco vco reg ramp gen ramp_out ramp_set aux reg pu_vco pu_reg gnd_vco d/a i_cpsw dect single-chip transceiver t2801 preliminary rev. 4567a?dect?01/03
2 t2801 4567a?dect?01/03 pin configuration figure 2. pinning hp-vfqfp-n48 clock data enable ref_clk ld pu_reg vs_pll vreg reg_ctrl vs_reg gnd_cp vs_cp ramp_out if_in2 if_in1 vs_if tx_out gnd3 rf_in2 rf_in1 gnd2 if_tank2 if_tank1 rssi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 t2801 r x _ o n t x _ o n m i x e r _ o u t 1 p u _ v c o t x _ d a t a v s _ m i x e r g n d _ p l l p u _ r x / t x p u _ p u l l i _ c p s w r a m p _ s e t m i x e r _ o u t 2 c p g n d _ v c o v s _ v c o g n d 1 v t u n e v r e g _ v c o b b _ o u t d a c _ d e c b b _ c f r e g _ d e c d e m o d _ t a n k 2 d e m o d _ t a n k 1
3 t2801 4567a?dect?01/03 functional block description name description aux reg auxiliary voltage regulator bbf baseband filter cp charge pump dac d/a converter for demodulator tuning demod demodulator gf gaussian filter for transmit data if amp1 1st intermediate frequency amplifier if amp2 2nd intermediate frequency amplifier ir mixer image rejection mixer mcc modulation compensation circuit pc programmable counter pd phase detector ramp gen ramp-signal generator rc reference counter rssi received signal-strength indicator tx driver buffer amplifier for tx_out tx/rx switch switches vco signal to ir mixer resp. tx driver vco voltage-controlled oscillator vco reg voltage regulator for vco pin description pin symbol function configuration 1 2 3 clock data enable 3-wire-bus: clock input 3-wire-bus: data input 3-wire-bus: enable input clock data enable 1,2,3 5k 5k vs_pll 7 gnd_pll 43
4 t2801 4567a?dect?01/03 4 ref_clk reference-frequency input 5 ld lock-detect output 6pu_reg power-up input for auxiliary voltage regulator 7 vs_pll pll supply voltage pin description (continued) pin symbol function configuration vs_pll 7 ref_clk 4 10k gnd_pll 43 10k gnd_pll 43 100 ld 5 pu_reg 6 25k 25k gnd_pll 43 gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7
5 t2801 4567a?dect?01/03 8 9 10 vreg reg_ctrl vs_reg auxiliary voltage-regulator output auxiliary voltage-regulator control output auxiliary voltage-regulator supply voltage 11 12 13 gnd_cp vs_cp cp charge-pump ground charge-pump supply voltage charge-pump output 14 15 16 vs_vco vreg_vco gnd_vco vco voltage-regulator supply voltage vco voltage-regulator control output vco ground pin description (continued) pin symbol function configuration vreg 8 reg_ctrl 9 vs_reg 10 gnd_pll 43 vs_pll 7 vs_cp 12 cp 13 gnd_cp 11 vs_pll 7 gnd_pll 43 vs_vco 14 gnd_vco 16 vreg_vco 15 vs_pll 7 gnd_pll 43
6 t2801 4567a?dect?01/03 17 vtune vco tuning voltage input 18 gnd1 ground 19 20 demod_tank1 demod_tank2 demodulator tank circuit demodulator tank circuit pin description (continued) pin symbol function configuration vtune 17 gnd_vco 16 vreg_vco 15 vs_pll 7 gnd_pll 43 gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 demod tank1 19 10k 10k demod tank2 20 vs_mixer 42 gnd1 18 vs_if 33 gnd2 28
7 t2801 4567a?dect?01/03 21 dac_dec decoupling pin for vco_dac 22 reg_dec decoupling pin for vco_reg 23 bb_cf baseband filter corner-frequency control input 24 bb_out baseband filter output pin description (continued) pin symbol function configuration dac_dec 21 10k gnd_vco 16 400 vreg_vco 15 vs_pll 7 gnd_pll 43 reg_dec 22 42k 2k vreg_vco 15 gnd_vco 16 vs_if 33 gnd2 28 bb_cf 23 vs_if 33 gnd1 18 gnd2 28 vs_if 33 gnd1 18 bb_out 24 gnd2 28
8 t2801 4567a?dect?01/03 25 rssi received signal-strength indicator output 26 27 if_tank1 if_tank2 if tank circuit if tank circuit 28 gnd2 ground pin description (continued) pin symbol function configuration vs_if 33 rssi 25 13k gnd2 28 vs_if 33 rssi 25 13k gnd2 28 gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7
9 t2801 4567a?dect?01/03 29 30 rf_in1 rf_in2 rf input of image reject mixer rf input of image reject mixer 31 gnd3 ground 32 tx_out tx driver amplifier output for pa pin description (continued) pin symbol function configuration rf_in1 29 gnd2 28 vs_mixer 42 rf_in2 30 gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 tx_out 32 gnd3 31
10 t2801 4567a?dect?01/03 33 vs_if if amplifier supply voltage 34 35 if_in1 if_in2 if input of if amplifier if input of if amplifier 36 ramp_out ramp-generator output for pa power ramping pin description (continued) pin symbol function configuration gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 if_in1 34 if_in2 35 4.3k vs_if 33 gnd2 28 vs_mixer 42 gnd2 28 ramp_out 36 vs_if 33
11 t2801 4567a?dect?01/03 37 ramp_set slew-rate setting of ramping signal 38 39 rx_on tx_on rx control input tx control input 40 41 mixer_out1 mixer_out2 mixer output to saw filter mixer output to saw filter pin description (continued) pin symbol function configuration 100 ramp set 37 vs_mixer 42 gnd2 25 1k vs_if 33 rx_on tx_on 38, 39 5k 5k vs_if 33 gnd1 18 gnd2 28 270 270 mixer_ out2 41 mixer_ out1 40 gnd2 28 vs_mixer 42 vs_if 33
12 t2801 4567a?dect?01/03 42 43 vs_mixer gnd_pll mixer supply voltage pll ground 44 pu_vco vco power-up input 45 pu_rx/tx rx/tx power-up input pin description (continued) pin symbol function configuration gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 pu_vco 44 5k 5k vs_vco 14 gnd_vco 16 gnd_pll 7 pu_rx/tx 45 gnd1 18 25k 25k gnd_pll 7
13 t2801 4567a?dect?01/03 46 pu_pll pll power-up input 47 tx_data tx data input of gaussian filter and modulation-compensation circuit 48 i_cpsw charge pump switch input controls charge pump current pin description (continued) pin symbol function configuration pu_rx/tx 45 gnd1 18 25k 25k gnd_pll 7 tx_data 47 5k 5k vs_pll 7 gnd_pll 43 i_cpsw 48 5k vs_pll 7 gnd_pll 43
14 t2801 4567a?dect?01/03 functional description receiver the rf signal at rf_in is fed to an image rejection mixer ir_mixer with its differential outputs mixer_out1 and mixer_out2 driving an if-saw filter at 110.592 mhz or 112.32 mhz. the if amplifiers if_amp1 and if_amp2 with an external if_tank and an integrated rssi function feed the signal to the demodulator demod working at f = f if /2 ([55 mhz) and finally to an integrated baseband filter bb. for demodulator tuning in production, an integrated 5-bit digital-to-analog (d/a) converter is provided to control the on-chip varicap diode. transmitter the transmit data at tx_data is filtered by an integrated gaussian filter (gf) and fed to the fully integrated vco operating at twice the output frequency. after modulation, the signal is frequency-divided by 2 and fed via a tx/rx switch to the tx_driver. this bus-controlled driver amplifier supplies typical +3 dbm output power at tx_out. an integrated ramp-signal generator, ramp_gen, provides a ramp signal at ramp_out for the external power amplifier. the slope of the ramp signal is controlled by a capacitor at the ramp_set pin. synthesizer the ir_mixer, the tx_driver and the programmable counter pc are driven by the fully integrated vco (including on-chip inductors and varactors). an 3-bit digital-to-ana- log converter is used to pretune the frequency. the output signal is frequency-divided to supply the desired frequency to the tx_driver, 0/90 degree phase shifter for the ir_mixer and to be used by the pc for the phase detector pd (f pd = 3.456 mhz). unlimited multislot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit mcc. power supply an integrated bandgap-stabilized voltage regulat or for use with an external low-cost pnp transistor is implemented. multiple power-down and current saving modes are provided.
15 t2801 4567a?dect?01/03 figure 3. pll principle rf_in programable counter pc "- main counter mc "- swallow counter sc f vco = f pd x (s mc x 32 + s sc ) f vco phase frequency divider by 2 pa driver detector pd vco mixer vco dac f pd = 3.456 mhz gf_data controlled phase shifting modulation gaussian compensation mcc filter gf reference counter rc 6.912 mhz ref_clk s mc 13.824mhz 4 20.736mhz 6 1.152 mbit/s pll reference tx_data frequency ref_clk baseband controller 3 10.368mhz ext. loop filter charge pump
16 t2801 4567a?dect?01/03 table 1 shows the lo frequencies for rx and tx for the dect band plus additional channels for the extended dect band. intermediate frequencies of 110.592 mhz and 112.32 mhz are supported. table 1. lo frequencies formula : tx: f ant = f vco = 1.728 mhz x (32 x s mc + s sc ) rx: f ant = 1.728 mhz x (32 x s mc + s sc ) + f if mode f if /mhz channel f ant /mhz f vco /mhz s mc s sc tx c9 1881.792 1881.792 34 1 tx c8 1883.520 1883.520 34 2 tx ... ... ... ... ... tx c1 1895.616 1895.616 34 9 tx c0 1897.344 1897.344 34 10 tx c10 1899.072 1899.072 34 11 tx c11 1900.800 1900.800 34 12 tx ... ... ... ... ... tx c29 1931.904 1931.904 34 30 tx c30 1933.632 1933.632 34 31 rx 110.592 c9 1881.792 1771.200 32 1 rx 110.592 c8 1883.520 1772.928 32 2 rx 110.592 ... ... ... ... ... rx 110.592 c1 1895.616 1785.024 32 9 rx 110.592 c0 1897.344 1786.752 32 10 rx 110.592 c10 1899.072 1788.480 32 11 rx 110.592 c11 1900.800 1790.208 32 12 rx 110.592 ... ... ... ... ... rx 110.592 c29 1931.904 1821.312 32 30 rx 110.592 c30 1933.632 1823.040 32 31 rx 112.320 c9 1881.792 1769.472 32 0 rx 112.320 c8 1883.520 1771.200 32 1 rx 112.320 ... ... ... ... ... rx 112.320 c1 1895.616 1783.296 32 8 rx 112.320 c0 1897.344 1785.024 32 9 rx 112.320 c10 1899.072 1786.752 32 10 rx 112.320 c11 1900.800 1788.480 32 11 rx 112.320 ... ... ... ... ... rx 112.320 c29 1931.904 1819.584 32 29 rx 112.320 c30 1933.632 1821.312 32 30
17 t2801 4567a?dect?01/03 control signals table 2. control signals ? functions table 3. control signals ? modes signal function i_cpsw controls the charge pump current pu_reg activates aux voltage regulator supplying the complete transceiver pu_vco activates vco voltage regulator which supplies only the vco pu_rx/tx activates rx/tx blocks pu_pll activates pll circuits: pc, pd, cp, rc rx_on activates rx circuits: bbf, demod, if amp, ir mixer tx_on activates tx circuits: tx?driver, ramp gen. starts ramp signal at ramp out data word 1, bit d10 activates gf in tx mode data word 1, bit d9 activates mcc in tx mode mode tx mode rx mode rssi only pu_reg 111 pu_vco 111 pu_rx/tx 111 pu_pll 111 rx_on 011 tx_on 101 bb filter off on off demodulator off on off if amplifiers and rssi off on on ir mixer off on on rx switch off on on tx switch on off off tx driver on off off ramp generator on off off programmable counter on on on voltage-controlled oscillator on on on gaussian filter on off off phase detector/charge pump on on on modulation compensation circuit on off off reference counter on on on typical current consumption/ma at v s = 3.2 v 54 85 80
18 t2801 4567a?dect?01/03 serial programming bus the transceiver is programmed by the 3-wire bus (clock, data and enable). after setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the msb-bit. after enable returning to high condition, the programmed information is loaded into the addressed latches, according to the addressbit condit ion (last bit). additi onal leading bits are ignored and there is no check made on how many pulses arrived during enable-low con- dition. during enable low condition, the bus current is increased to speed up the bus logic. the programming of the transceiver is separated into two data words. data word 1 con- trols mainly the channel information together with settings, which are closely related with the channel. data word 2 holds setup information, which is adjusted during production. data word 1 data word 2 data word 1 programs pll settings with the reference counter bits d21-d22 with the main counter bits d14-d15 msb lsb data bits address bit d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a0 rc sc mc vcos 1 1 gf mcc gfcs vcodac cpcs gf 1 e10 e9e8e7e6e5e4e3e2e1e0 a0 demoddac mccs test 0 rc (referene counter) d22 d21 s rc ref_clk (mhz) 00310.638 01413.824 10620.736 mc (main counter) d15 d14 s rc 0032 0133 1034 1135
19 t2801 4567a?dect?01/03 with the swallow counter bits d16-d20 vco select (rx/tx vco) with bit d13 used to switch between rx/tx vco gaussian filter on/off with bit d10 gf is used only in tx mode modulation compensation circuit on/off with bit d9 mcc is used only in tx mode gfcs adjustment with bit d6 - d8 only in txmode effective for setting the frequency deviation of the modulation sc (swallow counter) d20 d19 d18 d17 d16 s sc 000000 000011 000102 ... ... 1110129 1111030 1111131 d13 vcos (vco select) 0 rx-vco 1 tx-vco d10 gf (gaussian filter) 0off 1on d9 mcc (modulation compensation circuit) 0off 1on gfcs(gaussian filter settings) d8 d7 d6 gfcs (%) 00060 00170 01080 01190 1 0 0 100 1 0 1 110 1 1 0 120 1 1 1 130
20 t2801 4567a?dect?01/03 vco_dac adjustment with bit d3 - d5 used to pretune the vco frequency in case of production tolerances of the device. tun- ing voltage in locked condition should be around 1.8 v at room temperature. this gives margin for ambient temperature changes. cpcs adjustment with bit d0 - d2 used to adjust the charge pump current. this can be used to compensate the change of the tuning sensitivity over frequency and device tolerances. data word 2 programs demoddac adjustment with bits e6 - e10 only in rx mode effective. used to tune the demodulator center frequency and allows to compensate tolerances of extenal components and the t2801. pretune dayc voltage d5 d4 d3 f vco /% 000-5 0 0 1 ... 0 1 0 ... 0 1 1 ... 1 0 0 ... 1 0 1 ... 1 1 0 ... 1115 cpcs (charge-pump current settings) d2 d1 d0 cpcs 000-4 001-3 010-2 011-1 1000 1011 1102 1113 demod dac voltage e10 e9 e8 e7 e6 f ifcenter (%) 00000 -5 00001 ... 00010 ... ... 11101 ... 11110 ... 11111 5
21 t2801 4567a?dect?01/03 mccs adjustment with bits e3 - e5 only in tx mode effective. adjusts the modulation compensation circuit for closed loop modulation. this adjustment is done with a test sequence of a long stream of ,1' - ,0'. the correct setting is achieved, if the modulation is not affected by the pll. test mode settings with bit e0 - e2 and d11 in normal operation lock detect output is used. all other settings are for test only. figure 4. 3-wire bus protocol timing diagram table 4. 3-wire bus protocol mccs (modulation compensation settings) e5 e4 e3 mccs (%) 00060 00170 01080 01190 100100 101110 110120 111130 d11 e2 e1 e0 signal at lock detect output cp mode 1 0 0 0 lock detect active 0 0 0 1 rc out/2 active 1 0 1 0 pc out/2 active x 0 1 1 mcctest: rc out diviced by 512 active 1 1 0 0 lock detect high imp. 0 1 0 1 rc out/2 high imp. 1 1 1 0 pc out/2 high imp. x111gftest: rc out high imp. description symbol minimum value unit clock period tper 125 ns set time data to clock ts 60 ns hold time data to clock th 60 ns clock pulse width tc 60 ns set time enable to clock tl 200 ns hold time enable to data tec 0 ns time between two protocols tt 250 ns data clock enable tt tec ts tc th tl tper
22 t2801 4567a?dect?01/03 figure 5. tx data timing table 5. tx data timing values parameters symbol value remarks set-up time tx data ts 10 ns ts and th must be considered for both (falling and rising) edges of refclk when using ref_clk = 10.368 mhz. hold time tx data th 10 ns refclk tx_data t s t h absolute maximum ratings all voltages refer to gnd parameters symbol min. max. unit supply voltage regulator, pin 10 v s_reg 3.2 4.7 v supply voltage, pins 7, 12, 14, 33 and 42 v s 3.0 4.7 v logic input voltage, pins 1, 2, 3, 38, 39, 44, 45, 46, 47 and 48 v in -0.3 v s v junction temperature t jmax 150 c storage temperature t stg -40 +150 c thermal resistance parameters symbol value unit junction ambient r thja tbd k/w operating range parameters symbol min. typ. max. unit supply voltage regulator, pins 10 v s_reg 3.2 3.6 4.6 v supply voltage, pins 7, 12, 14, 33 and 42 v s 3.0 3.0 4.6 v ambient temperature t amb -25 +85 c
23 t2801 4567a?dect?01/03 electrical characteristics test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25c parameters test conditions/pins symbol min. typ. max. unit ir mixer pins 29, 30, 40 and 41 input impedance pins 29 and 30 z in 50 input matching pins 29 and 30 vswr in <2:1 image rejection ratio pins 40 and 41 irr 20 db dsb noise figure pins 40 and 41 nfdsb= nfssb 10 db conversion gain rload = 200 g conv 11 db input interception point pins 40 and 41 iip3 -10 dbm if amplifier pins 26, 27, 34 and 35 input impedance pins 34 and 35 z in 200 400 lower cut-off frequency fl 3db 90 mhz upper cut-off frequency fu 3db 130 mhz power gain gp 85 db bandwidth of external tank circuit pins 26 and 27 bw3db 10 mhz noise figure nf 9 db rssi pins 25, 34 and 35 rssi sensitivity at if_in1, if_in2 pins 34 and 35 p min 20 dbv rssi compression at if_in1, if_in2 pins 34 and 35 p max 100 dbv rssi dynamic range dr 80 db rssi resolution slope of the rssi has to be steady acc 2db rssi rise time p in = 30 to 100 dbv, pin 25 t r 1s rssi fall time p in = 100 to 30 dbv, pin 25 t f 1s quiescent output voltage at p in < 20 dbv at if_in1, if_in2 pin 25 i out 0.45 a maximum output voltage at p in = 100 dbv at if_in1, if_in2 pin 25 i out 2.25 a fm demodulator, bb-filter pins 19, 20, 23 and 24 co-channel rejection ratio at p in = -75 dbm at ir-mixer input ccrr 10 db sensitivity quality factor of external tank circuit approximately 20, f res =f if /2, pin 24 s0.5v/mhz amplitude of recovered signal nominal deviation of signal 288khz, pin24 a 450 mvss corner frequency pin 23: c = 68 pf f c 680 khz output voltage dc range pin 24 v outdc 1vs-1v dac for fm demodulator (internally connected) demod_dac range (see bus protocol e6 ... e10) f ifcenter 5%
24 t2801 4567a?dect?01/03 vco rx-vco frequency range vcos = ?0? bit d13 f vco 1769 1824 mhz tx-vco frequency range vcos = ?1? bit d13 f vco 1881 1934 mhz tuning gain g tune 40 mhz/v frequency control voltage range pin 17 v tune 0.4 2.8 v vco_dac range (see bus protocol d3 ... d5) f vco,dac 5% pll scaling factor prescaler s psc 32/33 scaling factor main counter s mc 32/33/34/35 scaling factor swallow counter s sc 031 external reference input frequency ac coupled sinewave pin 4 f ref_clk 10.368 13.824 20.736 mhz mhz mhz external reference input voltage ac coupled sinewave pin 4 v ref_clk 50 250 mv rms scaling factor reference counter s rc 3/4/6/8 charge pump pin 13 output current v cp = v vs_cp / 2, i_cpsw = ?1? pin 48 i cp_nom 6.5 ma output current v cp = v vs_cp / 2, i_cpsw = ?0? pin 48 i cp_nom 1.2 ma current scaling i cp = i cp_nom + cpcs * i cp_step (see bus protocol d0 ... d2) i cp_step 0.2 ma leakage current i l 100 pa gaussian transmit filter (gaussian shape b ? t = 0.5) tx data filter clock 12 taps in filter f txfclk 13.824 mhz frequency deviation gf fm_nom 350 khz frequency deviation scaling gf fm = gf fm_nom * gfcs (see bus protocol d6 ... d8) gfcs 60 130 % modulation compensation circuit oversampling ovs 6 digital sum variation dsv 85 current scaling factor (see bus protocol e3 ... e5) mccs 60 130 % vco switch and tx driver pin 32 power gain at p in = -40 dbm gp 30 db output impedance pin 32 z out 100 maximum output power pin 32 p max 03 dbm gain compression at tx_rf_out, pin 32 p 1db 1dbm output interception point pin 32 oip3 10 dbm ramp generator pins 36 and 37 minimum output voltage according to ramp_set input v min 0.7 v electrical characteristics (continued) test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25c parameters test conditions/pins symbol min. typ. max. unit
25 t2801 4567a?dect?01/03 maximum output voltage according to ramp_set input v max 2.2 v rise time c ramp = 270 pf at pin 37 t r 5s fall time c ramp = 270 pf at pin 37 t f 5s lock detect and test mode output pin 5 lock detect output, test mode output locked = ?1?, unlocked = ?0? test modes (see bus protocol e0 ... e2) ld leakage current v oh = 4.6 v i l 5a saturation voltage i ol = 0.5 ma v sl 0.4 v auxiliary regulator pins 8, 9 and 10 output voltage v sreg = 3 v pin 8 v reg 2.9 3.0 3.1 v supply voltage rejection v pin10 = v dc + 0.1 v pp f pin10 = 0.1 to 10 khz c pin8 = 100 nf svr tbd db vco regulator pins 14, 15 and 12 output voltage v svco = 3 v pin 15 v reg_vco 2.6 2.7 2.8 v 3-wire bus clock f clock 6.912 mhz logic input levels (clock, data, enable, rx_on, tx_on, pu_vco , tx_data, i_cpsw), pins 1, 2, 3, 38, 39, 44, 47 and 48 high input level = ?1? v ih 1.5 v low input level = ?0? v il 0.5 v high input current = ?1? i ih -5 5 a low input current = ?0? i il -5 5 a standby control pins 6, 45 and 46 power up pu_reg = ?1? pu_rx/tx = ?1? pu_pll = ?1? high input level pin 6 pin 45 pin 46 vpu_reg vpu_rx/tx vpu_pll 2.0 v standby pu_reg = ?0? pu_rx/tx = ?0? pu_pll = ?0? low input level pin 6 pin 45 pin 46 vpu_reg,off vpu_rx/tx,of f vpu_pll,off 0.7 v power up pu_reg = ?1? pu_rx/tx = ?1? pu_pll = ?1? high input current vpu = 3 v, pin 6 vpu = 5.5 v, pin 45 vpu = 3 v, pin 46 vpu = 5.5 v ipu_reg ipu_rx/tx ipu_pll 20 60 100 200 30 80 125 300 40 100 150 400 a a a a standby pu_xxxx = ?0? low input current vpu = 0 v, pin 6, vpu = 0.5 v, pins 45, 46 ipu,off 0.1 1 a a electrical characteristics (continued) test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25c parameters test conditions/pins symbol min. typ. max. unit
26 t2801 4567a?dect?01/03 settling time v s = 0 active operation switched from v s = 0 to v s = 3v t soa < 10 s settling time standby active operation switched from pu = ?0? to pu = ?1? t ssa < 10 s settling time aactive operation standby switched from pu = ?1? to standby t sas < 2 s power supply pins 7, 10, 12, 14, 33 and 42 total supply current rx i s 85 ma total supply current rssi only i s 82 ma total supply current tx i s 54 ma total supply current tx (mcc, gf active) i s 58 ma standby current pu_rx/tx = gnd i s 10 a supply current cp v vs_cp = 3 v, pll in lock condition, pin 13 i cp 1a electrical characteristics (continued) test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25c parameters test conditions/pins symbol min. typ. max. unit
27 t2801 4567a?dect?01/03 figure 6. t2801 aplication circuit vcc bb_out rssi 48 i_cpsw 47 tx_data 46 pu_pll 45 pu_rx/tx 44 pu_vco 43 gnd_pll 42 vs_mixer 41 mixer_out2 40 mixer_out1 39 tx_on 38 rx_on 37 ramp_set cp 13 vs_vco 14 vreg_vco 15 gnd_vco 16 vtune 17 gnd1 18 demod_tank1 19 demod_tank2 20 dac_dec 21 reg_dec 22 bb_cf 23 bb_out 24 1 2 v s _ c p 1 1 g n d _ c p 1 0 v s _ r e g 9 r e g _ c t r l 8 v r e g 7 v s _ p l l 6 p u _ r e g 5 l d 4 r e f _ c l o c k 3 e n a b l e 2 d a t a 1 c l o c k r s s i 2 5 i f _ t a n k 1 2 6 i f _ t a n k 2 2 7 g n d 2 2 8 r f _ i n 1 2 9 r f _ i n 2 3 0 g n d 3 3 1 t x _ o u t 3 2 v s _ i f 3 3 i f _ i n 1 3 4 i f _ i n 2 3 5 r a m p _ o u t 3 6 pu_vco pu_rx/tx pu_pll tx_data i_cpsw tx_on rx_on ld pu_reg clock data enable ref_clk bc808 or similar 560 pf 220 pf 15 pf 15 pf 270 nh 33 pf 33 pf 180 nh 56 pf 470 nf 180 w 150 nf 22 nf 68 pf 2.2 nf 100 pf tbd tbd 18 pf 100 nh tx_ou t rf_in saw filter tfs 112b tantal tantal 4.7 nf ramp_out 68 pf t2801
28 t2801 4567a?dect?01/03 package information ordering information extended type number package remarks t2801-plh hp-vfqfp-n48 taped and reeled
printed on recycled paper. ? atmel corporation 2003. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change de vices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, ex pressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4567a?dect?01/03 xm atmel ? is the registered trademark of atmel. other terms and product names may be the trademarks of others.

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